1. Field of the Invention
The present invention relates to semiconductor memory devices and pad arranging methods thereof, and more particularly, to a pad arrangement capable of easily coping with an increase in the number of pin terminals.
2. Description of the Background Art
FIG. 11 shows an arrangement of pads and a lead frame of a conventional dynamic random access memory (DRAM). In FIG. 11, a required circuit is formed on a semiconductor chip CH having a rectangular shape with a longer side (a first side) and a shorter side (a second side). Although not clearly shown in FIG. 11, a memory cell array, an input/output buffer, and a control circuit are formed in the semiconductor memory device. A central region CR is formed to extend along the longer side at the central portion with respect to the shorter side of semiconductor chip CH. In central region CR, pads PD for making electrical connection to a chip outside are alignedly arranged in a line.
Lead frame FL is arranged for connecting to pads PD and extending to be external pin terminals. Generally, leads are supported by a frame (metal frame) in a lead frame, and lead portions are cut off from the frame after semiconductor chip CH is sealed with resin. Each lead portion will be referred to as a frame lead in the description made hereinafter. Each frame lead FL extends over semiconductor chip CH to the vicinity of central region CR, where it is connected with a corresponding pad PD through a bonding wire (not shown). After the bonding step is completed, the semiconductor memory device is sealed with resin and put in a package PA. Thereafter, the respective other ends of the frame leads are cut off from the frame and machined in accordance with the shape of pins of the pin arrangement of the package and they serve as external pin terminals.
The structure in which frame leads extend to the central portion of semiconductor chip CH as shown in FIG. 11 is called an LOC (Lead On Chip) structure. In the LOC structure, pads PD are arranged in central region CR of semiconductor chip CH. As compared with a commonly used structure of peripheral pad arrangement in which pads are arranged along the longer sides at both ends of the shorter side of the semiconductor chip CH, the area occupied by the pads can be reduced and therefore semiconductor chip CH is shortened in the direction of its shorter side in LOC structure.
Generally, development of semiconductor memory devices such as a DRAM begins with less bit products having a small bit width of data such as .times.1 bit and .times.4 bits. Based on the less bit product thus developed, development of multiple bit products such as .times.8 bits and .times.16 bits (referred to as multiple bit expansion) is carried out. Semiconductor memory devices are advanced to have more storage capacity, and a DRAM with a storage capacity of 256M bits or more is developed at present. For a DRAM with such a large storage capacity, multiple bit products of .times.32 bits or more must be developed in accordance with the data width of an external processor (in accordance with the word length). In such a multiple bit product, the numbers of data input/output pins, address signal input pins and control signal input pins are increased in accordance with increase in the number of data bits and in storage capacity, and thus at least 80 pin terminals are necessary.
If pads PD are alignedly arranged in a line in central region CR as shown in FIG. 11 when at least 80 pin terminals are necessary, the longer side of semiconductor chip CH is increased in length because each pad corresponds with an external pin terminal. Therefore, in this case, the chip length (the length of the longer side of semiconductor chip CH) is determined by the pitch between pads PD (the distance between the central portions of pads) and the number of pads, not by the length of semiconductor chip CH required to form circuitry to be formed in semiconductor chip CH. As a result, if the pitch between pads PD cannot be reduced, the longer side of semiconductor chip CH becomes longer unnecessarily for only the disposal of pads PD, giving rise to a problem of an increase in size of the chip. The pitch between pads PD must be reduced in order to suppress such an increase in size of semiconductor chip CH. However, a novel technique which is completely different from a conventional one must be developed for this purpose, and it is difficult to reduce the pitch between pads PD at present.
If package PA of a semiconductor memory device is of an SOP (Small Outline Package) type or a TSOP (Thin Small Outline Package) type where lead pins are taken out only from the both longer sides of package PA as shown in FIG. 11 or of an SOJ (Small Outline J-leaded package) type, the length of the longer side of package PA is determined by the pitch between pin terminals (the portions of frame leads FL outside the package) and the number of pin terminals, not by the length of the longer side of semiconductor chip CH contained therein. Therefore, if the pitch between the pin terminals cannot be reduced, the package size is increased. For reduction of the pitch between the pin terminals, working accuracy and insulation characteristics of the leads, among others, must be considered, and there is a limit to such a reduction. A novel technique which is completely different from a conventional one is required to sufficiently reduce the pitch between the pin terminals without causing an increase in size of the package, which is difficult at present.